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-- Company: 
-- Engineer: 
-- 
-- Create Date:    10:15:52 11/23/2017 
-- Design Name: 
-- Module Name:    counter10 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity counter10 is
    Port ( clk : in  STD_LOGIC;
           carryin : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           carryout : out  STD_LOGIC;
           timeout : out  STD_LOGIC_VECTOR (3 downto 0));
end counter10;

architecture Behavioral of counter10 is
signal cnt:STD_LOGIC_vector(3 downto 0):="0000";
begin

process(clk,reset)
begin
if reset='1' then
     cnt<="0000";
     else
     if clk'event and clk='1' then
       if carryin='1' then
         if cnt="1001" then
           cnt<="0000";
       else
      cnt<=cnt+1;
     end if;
      else
     null;
    end if;
   end if;
end if;
end process;
timeout<=cnt;
carryout<='1' when carryin='1' and cnt="1001" else '0';
end Behavioral;